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data brief for further information contact your local stmicroelectronics sales office. march 2009 rev 2 1/14 14 sta8058 teseo? high performance gps multichip module (mcm) features gps multichip module: ? sta2058 teseo baseband ? sta5620 rf front-end complete embedded memory system: ? flash 256 kb + 16 kbytes ? ram 64 kbytes. 66-mhz arm7tdmi 32 bit processor high performance gps engine (hpgps) sbas (waas and egnos) supported sensitivity (-146 dbm acquisition, -159 dbm tracking) time to first fix (1 s reacquisition, 2.5 s hot start, 34 s warm start, 39 s cold start) accuracy (2 m autonomous) extensive gps receiver interfaces: 32 gpios, 4 uarts, 2 spis, 2 i2cs, 1cans 2.0, 1 usb 1.1, 1 hdlc and 4 channels adc compatible with l1 signal (c/a code) st proprietary technology ? cmos flash embebbed technology for sta2058 ? bicmos sige technology for sta5620 lfbga104 lead-free package -40 c to 85 c operating temperature range evaluation kits sta8058 module reference designs (17x19 mm and 25x25 mm) evaluation board hosting sta8058 module description sta8058 teseo mcm is a fully embedded gps engine integrating sta2058 teseo baseband. and sta5620 rf front-end. the embedded flash memory enables the equipment manufacturer to load the entire gps software (including tracking, acquisition, navigation and data output) after customising its interfaces to his needs. a standard gps library is available from st. by combining the arm7tdmi microcontroller core with on-chip flash/ram, 16-channel gps correlator dsp, rf front-end and an extensive range of interfaces on single package solution, the sta8058 provides a highly-flexible and cost- effective solution for gps applications. lfbga104 (7x11x1.4 mm) table 1. device summary order code package packing automotive grade sta8058 lfbga104 (7x11x1.4mm) tray no STA8058TR lfbga104 (7x11x1.4mm) tape and reel no sta8058a lfbga104 (7x11x1.4mm) tray yes sta8058atr lfbga104 (7x11x1.4mm) tape and reel yes www.st.com
contents sta8058 2/14 contents 1 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 lfbga104 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
sta8058 features summary 3/14 1 features summary arm7tdmi 16/32 bit risc cpu based host mi crocontroller running at a frequency up to 66 mhz. complete embedded memory system: ? flash 256 kbytes + 16 kbytes (100 kb erasing/programming cycles) ? ram 64 kbytes. 16 channel high performance gps correlation dsp. st propietary technology: ? cmos flash embedded technology for baseband ? bicmos sige for radio front-end sbas (waas and egnos) supported. -40 c to 85 c operating temperature range. 104-pin lfbga104 package. power supply: ? 3.0 v to 3.6 v operating supply range for input/output periphery ? 3.0 v to 3.6 v operating supply range for a/d converter reference ? 1.8 v operating supply range for core supply provided by internal voltage regulator with external stabilization capacitor or by external supply voltage ? 2.4 v to 3 v operating supply range for rf front-end section reset and clock control unit able to provide low power modes (wait, slow, stop, standby) and to generate the internal clock from the external reference through integrated pll. 32 programmable general purpose i/o, each pin programmable independently as digital input or digital output; 30 are multiplexed with peripheral functions; 16 can generate an interrupt on input level/transition. real time clock module with 32 khz low powe r oscillator and separate power supply to continue running during stand-by mode. 16-bit watchdog timer with 8 bits presca ler for system reliability and integrity. one can module compliant with the can specific ation v2.0 part b (active) and bit rate can be programmed up to 1 mbaud. four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output compare, one pulse counter function, one pwm channel with selectable frequency each. 4 channels 12-bit sigma-delta analog to digital converter, single channel or multi channel conversion modes, single-shot or continuous conversion modes, sample rate 1 khz, conversion range 0-2.5v . three serial communication interfaces (uart) allow full duplex, asynchronous, communications with external devices, independently programmable tx and rx baud rates up to 625k baud. one uart adapted to suit smart card interface needs, for asynchronous sc as defined by iso 7816-3. it includes sc clock generation. two serial peripheral interfaces (spi) allow full duplex, synchronous communications with external devices, master or slave operation, max baud rate of 5.5mb/s. one spi may be used as multimedia card interface.
features summary sta8058 4/14 tw o i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz), 7/10 bit addressing modes. one i 2 c interface is multiplexed with one spi, so either 2 x spi + 1 x i 2 c or 1 x spi + 2 x i 2 c may be used at a time. enhanced interrupt controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. up to 2 maskable interrupts may be mapped on fiq. wake-up unit allows exiting from powerdown modes by detection of an event on two external pins (one is active high and other is active low) or on internal real time clock alarm. usb unit v1.1 compliant, software configurable endpoint setting, usb suspend/resume support high level data link controller (hdlc) unit supports full duplex operating mode, nrz, nrzi, fm0 and manchester modes, and internal 8-bit baud rate generator. rf front-end features: ? low if (4 mhz) architecture ? compatible with gps l1 signal ? vga gain internally regulated ? on chip programmable pll ? spi interface
sta8058 pin description 5/14 2 pin description 2.1 logic symbol figure 1. sta8058 teseo mcm symbol avss ck spi (di,do,cs, clk) jtdi jtdo jtck jtms rstinn jtrstn rf_in booten v18bkp v18 [2] v33 [7] v27 [8] xtal (in,out,clk) avdd power clock & reset jtag port teseo gpsclk gpsdat pads vss [10] vssrf [11] rf pads sign gps_clk enable (chip,rf) mode if_test agc_cntr p0.[15:0] p1.[15:0] rtcxti rtcxto usbdp usbdn wakeup generai purpose i/o rtc usb pads & wkup pads nstdby_i mcm
pin description sta8058 6/14 2.2 system block diagram figure 2. sta8058 teseo baseband block diagram apb bridge3 5 dp 256k flash arm7td mi 64kram stc (jtag) arm7 native bus interrupt contr. 12-bit adc timer0 watch dog fully prog. i/o ports 5 dp uart0 4 af apb bridge2 1 dp 2 af 32 io timer1 4 af rtc 2 dp uart1 uart2 uart3 2 af 2 af 2 af 2 af hpgps 16-ch. correlator + emerald dsp [usb] 3 dp hdlc 3 af wakeup 16 af oscill [can] 2 af vreg 3 dp rccu pll i2c0 2 af i2c1 2 af apb bus apb bridge1 spi0 4 af apb bus timer2 2 af timer3 4 af 3 dp spi1 4 af
sta8058 pin description 7/14 figure 3. sta5620 rf front-end spi interface cp cmos dri ver s 2 bi ts combi ner rfa buffer xtal osc pfd / n ir mixer pol yphase filter if filt er gps_cl k / 48 0? 90? xtal_clk rf_en agc_ctrl rf_in mag sign / 2 / r spi_c s / spi_clk spi_di spi_d o mode si gn mag gp s_clk gc e xc e ad c xi x o test_en2 hc e lo48_clk gp s_clk sample_mode (1:0) lo96 variable xtal gc e & rfe enabl ed by rfe & sp eci fic enables reset gener at or reset if_tes t test_en1 test _clk sign mag agc if_out _en chip_en xt al_clk xt al_clk mag test lo gi c test_clk
pin description sta8058 8/14 figure 4. sta8058 teseo mcm block diagram rf_in sign gps_dat chip_en saw filter agc_cntr rf_en v27_rf [5] lna jtdi,jtck,jtms,jtrstn,jtdo sta8058 teseo mcm sta5620 rf front-end sta2058 baseband spi_di spi_do spi_clk s1_mosi s1_miso s1_sclk gps_clk ck xtal_in mode if_test v27_pll[4] vssrf [10] wake_up rtcxto rtcxti 3 timers [9], adc[4] the two dice must be interconnected eachother at board leve l spi[4], i2c[3], 3 uarts [6] usb[3], can[2], hdlc[3] p1.8/pps nrstin p1.9/prn boot0, boot1, booten nstdby_in v33 [4] v18[2] vss [4] v33io_pll v33_reg_bkp avdd v18bkp vss18[2] avss vss_bkp vss_reg vssio_pll xtal_clk gpsclk gpio gpio vssrf_a [2] vssrf_io tcxo v33 s1_ssn spi_cs
sta8058 pin description 9/14 2.3 lfbga104 ball out 2.4 power supply pins table 2. ball out for lfbga104 package 12345678 9 10111213 a vss avss avdd v18bkp rtcxto rtcxti v33re g_bkp gpsda t njtrst rf_en xtal_o ut xtal_in vssrf b p1.2/t3_ ocmpa/ ain.2 vss18 v18 vssbkp nstdby _in v33 vssre g gpscl k gps_clk chip_en v27pll v27pll v27pll c p1.1/t3_ icapa/ai n.1 p1.0/t3_ ocmpb/ ain.0 p1.4/t1 _icapa p1.5/t1_ icapb nrstin po.15/w akeup ck p0.5/s1 _mosi spi_di xtal_clk vssrf v27pll v27rf d v33io_p ll p1.3/t3_ icapb/ai n.3 p1.7/t1 _ocmp a vss vss jtck jtdo p0.6/s1 _sclk spi_clk mode vssrf vssrf vssrf_a e vssio_p ll p1.8/pp s p1.9/pr n.11 p1.6/t1_ ocmpb vss18 p0.13/u2 _rx/t2. ocmpa jtms jtdi spi_cs if_test vssrf vssrf rf_in f p1.11/ canrx usbdp p1.10/u sbclk p0.3/so _ssn/i1. sda v18 p0.14/u2 _tx/t2.i capa v33 p0.4/s1 _miso spi_do agc_cnt r vssrf vssrf vssrf_a g p1.12/ cantx usbdn p0.1/so _mosi/ u3.rx p0.0/so _miso/u 3.tx p0.7/s1_ ssn p0.9/uo _tx/bo ot.0 p0.11/u 1_tx/b oot.1 boote n sign v27rf v27rf v27rf vssrf h vss p1.13/h clk/io.s cl p1.14/h rxd/io. sda p1.15/ht xd p0.2/so _sclk/i1 .scl po.12/s cclk po.8/u o_rx/u 0.tx p0.10/u 1_rx/u 1.tx v33 vssrf:io v33 v27rf vssrf table 3. power supply pins symbol i/o function lfbga104 v 33 - digital supply voltage for i/o ci rcuitry (3.3 volt) b6,f7,g10,h9,h11 v ss - digital ground for i/o circuitry a1,d4,d5,h1 v 33io-pll - digital supply voltage for i/o circuitry and for pll reference (3.3v) d1 v ssio-pll - digital ground for i/o circuitry and for pll reference e1 v 33reg_bkp - digital supply voltage for backup block i/o circuitry and for ballast i/o (3.3v) a7 v ssreg - digital ground for ballast i/o b7 v 18 - digital supply voltage for core circuitry (1.8 volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 10 f (tantalum, low series resistance) + 33nf (ceram ic) shall be connected between these pins and v ss18 to guarantee on-chip voltage stability. b3,f5 v ss18 - digital ground for core circuitry b2,e5 v 18bkp - digital supply voltage for backup block (rtc, oscillator, wake-up controller - 1.8 volt): when using t he internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 1 f shall be connected between this pin and v ssbkp to guarantee on-chip voltage stability. a4
pin description sta8058 10/14 note: v 33 and v 33io-pll are all internally connected. same for v ss and v ssio-pll . all v ss , v ss18 , v ssbkp , av ss ,v ssrf ,v ssrf_a and v ssrf_io pins must be tied together to the common ground plane, taking care of noise filtering, especially on av ss , v ssrf , v ssrf_a and v ssrf_io v ssbkp - digital ground for backup logic b4 av dd - analog supply voltage for the a/d converter a3 av ss - analog supply ground for the a/d converter a2 v 27rf - analog supply voltage for rf chain (2.7v) c13,g10,g11,g12,h 12 v 27pll - analog supply voltage for pll embedded into rf part (2.7v) b11,b12,b13,c12 v ssrf - analog supply ground for rf core a13,c11,d11,d13, e11,e12,f11,f12, g13,h13 v ssrf_a - analog supply ground for rf amplifier d13, f13 v ssrf_io - analog supply ground for rf io circuirty h10 table 3. power supply pins (continued) symbol i/o function lfbga104
sta8058 electrical characteristics 11/14 3 electrical characteristics see sta2058 (teseo baseband) and sta5620 (rf front-end) datasheet for related data.
package information sta8058 12/14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 5. lfbga104 (11x7x1.4mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.400 0.0551 a1 0.210 0.0083 a2 0.990 0.0390 a3 0.200 0.0079 a4 0.800 0.0315 b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 10.900 11.000 11.100 0.4291 0.4331 0.4370 d1 9.600 0.3780 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 e1 5.600 0.2205 e 0.800 0.0315 f 0.700 0.0276 ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 lfbga104 l ow profile f ine pitch b all g rid a rray body: 11 x 7 x 1.4mm 8054244 b
sta8058 revision history 13/14 5 revision history table 4. document revision history date revision changes 25-oct-2007 1 initial release. 19-mar-2009 2 updated table 1: device summary on page 1 . updated ecopack description in section 4: package information on page 12 .
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